As a sort of computing architecture that incorporates the high flexibility of General Purpose Processors (GPPs) and the high efficiency of Application Specific Integrated Circuits (ASICs), reconfigurable computing architecture receives more and more attention in embedded system design in recent years, and the application fields of reconfigurable computing architecture mainly include multimedia processing, mobile communication, digital signal processing, and data encryption/decryption, etc. Granularity refers to the data bit width of the processing elements included in a reconfigurable system, and it determines the data processing capability of the reconfigurable system. Usually, granularities not exceeding 4 bits are referred to as fine granularities, while granularities exceeding 4 bits are referred to as coarse granularities. Reconfigurable systems can be classified into fine-grained reconfigurable systems and coarse-grained reconfigurable system according to the computed granularity. Since the computing units are configured at the operation level, coarse-grained reconfigurable systems can significantly reduce the overhead of system reconfiguration when compared with fine-grained reconfigurable systems.
As performance requirement and complexity of computation in media applications become increasingly higher, the computing resources required in coarse-grained reconfigurable architecture are increased in multiples. In some types of architecture, multiple reconfigurable arrays are employed to accomplish these applications. However, as the computing resources are increased, the volume of configuration information required in the reconfiguration process is further increased, resulting in further increased reconfiguration overhead of the system and severely degraded overall system performance. In the design of a coarse-grained reconfigurable system, the structure and management method for configuration information cache are key techniques, and determine the reconfiguration efficiency of dynamic system. Most configuration information cache management methods in conventional coarse-grained reconfigurable systems are designed with reference to the instructions cache management method of general purpose processor systems, without consideration of the characteristics of the hardware structure and specific application algorithm of the reconfigurable system. Consequently, the limited configuration information transmission capacity of the system does not match the powerful operating capacity, and can not meet the demanding requirement of the application algorithm for high performance.